Huawei unveils new ‘τ Scaling Law’ at IEEE ISCAS 2026, Aims to redefine semiconductor future beyond Moore’s Law

KATHMANDU: Chinese technology giant Huawei has introduced a new semiconductor development principle, dubbed the Tau (τ) Scaling Law, positioning it as a potential successor to the decades-old Moore’s Law amid mounting physical and economic constraints facing the global chip industry.

Speaking at the 2026 IEEE International Symposium on Circuits and Systems, Huawei executive He Tingbo delivered a keynote address titled “New Semiconductor Path in Practice”, outlining the company’s vision for the next phase of semiconductor advancement.

The announcement comes at a time when the semiconductor industry is grappling with slowing gains from transistor miniaturization, rising manufacturing complexity, and increasing costs. For more than five decades, Moore’s Law — the observation that transistor density doubles approximately every two years — has guided chip innovation. However, industry experts increasingly acknowledge that traditional geometric scaling is approaching fundamental physical limitations.

Huawei’s proposed τ Scaling Law seeks to replace geometric transistor shrinking with time (τ) scaling, focusing on reducing signal propagation delays across semiconductor systems. According to the company, the approach prioritizes improving performance, energy efficiency, and transistor density through systemic optimization rather than relying solely on increasingly smaller manufacturing nodes.

Logic Folding and Multi-Level Optimization

At the center of Huawei’s semiconductor strategy is a new architectural concept known as Logic Folding, which the company says can compress signal propagation delays and improve chip efficiency.

Huawei said it has developed a multi-level co-optimization framework spanning semiconductor devices, circuits, chips, and system architecture.

At the device level, Huawei aims to optimize transistor resistance and parasitic capacitance to reduce time constants at the physical layer, potentially improving processing efficiency.

At the circuit level, the Logic Folding architecture is designed to overcome physical limitations in traditional circuit layouts by shortening critical-path wiring, reducing resistive and capacitive loads, and increasing transistor density.

At the chip level, Huawei plans to integrate software, chip architecture, and silicon design through full-stack coordination to improve workload-based instruction and data flow management. The company claims this could significantly reduce execution time and improve parallel computing performance.

At the system level, Huawei is redefining interconnect protocols using what it calls a Unified Bus system to enable unified memory addressing and native memory semantics for high-performance computing clusters, known as SuperPoDs, reducing communication latency.

Kirin Chips to Adopt Logic Folding in 2026

Huawei disclosed that its next-generation Kirin chips, expected to launch in Fall 2026, will be the first processors to integrate the Logic Folding architecture. The company claims the move will significantly improve chip performance, although independent benchmarks and technical validations are yet to emerge.

According to He Tingbo, Huawei has already designed and mass-produced 381 chips over the past six years based on principles related to the τ Scaling Law, serving multiple sectors and industries.

The company further projected that by 2031, its high-end chips developed under the new scaling principle could achieve a transistor density equivalent to 14 angstrom (1.4 nanometer) manufacturing processes — a benchmark associated with next-generation semiconductor technology.

Global Semiconductor Race Intensifies

Huawei’s announcement arrives amid intensifying global competition in semiconductors, artificial intelligence (AI), and advanced computing. Major chipmakers worldwide are increasingly exploring alternatives to conventional scaling, including advanced packaging, chiplet architectures, AI accelerators, and new materials to sustain computational growth.

Industry observers say Huawei’s proposal reflects broader efforts to rethink semiconductor innovation pathways as computing demands surge due to AI workloads, cloud computing, smartphones, and next-generation digital infrastructure.

In her concluding remarks, He Tingbo emphasized international cooperation, stating that no single company can independently solve the future challenges of semiconductor evolution.

“We believe openness and collaboration are key to driving ongoing progress in the semiconductor industry,” she said, adding that Huawei intends to work with scientists, engineers, and global industry partners to promote sustainable semiconductor and electronics development.